1. Technological Field
The present technology relates to integrated circuit memory technology, and to word line driver configurations for integrated circuit memory.
2. Description of Related Art
High density memory devices are often laid out with high density memory in a memory area on a substrate, and peripheral circuits in a peripheral area on the substrate. The high density memory includes memory cells with word lines along the rows of memory cells, and bit lines along columns. The word lines are disposed in a patterned gate layer in the memory area, and the memory cells are connected to peripheral circuits using one or more patterned conductor layers over the patterned gate layer.
In large-scale systems, the memory arrays are often divided into array blocks and, as a result, the memory areas are divided into rows and columns of smaller areas. Some of the peripheral circuitry, such as word line drivers, is disposed in areas between the array blocks. In this manner, the word lines and other connectors used in each array block can connect to peripheral circuits along shorter lengths of conductors which can increase speed of operation, and save power.
Word line drivers operate with high speed in modern devices, and therefore require significant power levels. To achieve these goals, some memory architectures use global word line drivers and local word line drivers. The global word line driver is decoded to select an array block and to provide power signals to local word line drivers at each array block. A local word line driver is connected to each word line in an array block, and disposed adjacent to the array block. The local word line driver provides for selecting individual word lines within the array block utilizing the power signals from the global word line driver. One example of a local word line/global word line structure is described in United States Patent Application Publication No. US2013/0100758, entitled Local Word Line Driver, by Chen et al., published 25 Apr. 2013, which application is incorporated by reference as if fully set forth herein. In the example described in Publication No. US2013/0100758, both the local word lines and the global word lines are disposed in areas between the array blocks. Thus, while this configuration improves the efficiency of the distribution of power, and the speed of operation of the devices, it requires significant areas for peripheral circuitry to be disposed within the memory areas on the substrate. Also, the use of global word line drivers and local word line drivers increases the complexity of the patterned conductor layers. In high density circuitry, high complexity of patterned conductor layers can contribute to reductions in yield.
It is desirable to provide a compact and reliable architecture for memory devices utilizing global word line/local word line configurations.